The Interconnect Wall
Modern AI models are trained on thousands of GPUs working together as one machine. Since 2018, the biggest driver of AI training compute has been the number of chips in each cluster, which has grown 70% per year, outpacing gains in per-chip performance1. Microsoft’s newest Fairwater sites are built to link “hundreds of thousands of GPUs on a single flat network”2.
Every added chip needs links to the others, and those links are failing to pace with the scale of compute. Researchers at UC Berkeley found that over two decades, peak compute grew 60,000x while interconnect bandwidth grew only 30x3. As Mukesh Khare, general manager of IBM Semiconductors, put it, “the communication on how these chips can talk to each other is not keeping up”4.
Those links also draw serious power. At GTC 2025, Nvidia CEO Jensen Huang estimated that a one-million-GPU cluster would need about 6 million optical transceivers drawing 180 megawatts.5.
Meanwhile, copper is running out of reach. Copper cables are cheap and draw almost no power, but copper’s reach shrinks with every jump in speed. At 200 gigabits per lane, today’s standard, passive copper is specified to about one metre, down from three metres at 50G6. The industry’s current rule of thumb, as Ciena puts it, is “Copper when you can, optics when you must”7.
The bottleneck in AI hardware has shifted from computing data to communicating it.
From Pluggables to the Package
Inside an AI data centre, servers connect through layers of network switches, typically arranged as leaf-spine networks. Short links inside a rack run over copper. Longer links run over pluggable optical transceivers: finger-sized modules that slot into the front of a switch and convert electrical signals into light for high-performing communication.
However, traversing from the switch chip (which processes packets of information to and from the server) to the transceivers is a very loss-y process. Each module therefore carries a digital signal processor (DSP) to “rebuild” the original signal. In Nvidia’s breakdown of a 30-watt pluggable module, the DSP alone uses 20 watts8.
Co-packaged optics shortens that trip to a few millimetres by mounting small optical engines in the same package as the switch chip. Nvidia estimates electrical loss falls from up to 22 dB to about 4 dB9, and its 9-watt CPO port has no DSP at all: 2 watts for the laser and 7 for the optical engine8.
Lasers are the most heat-sensitive and failure-prone part of an optical link, so CPO designs move the laser back out to the front panel in swappable modules as an external source. The standard for those modules was developed at the Optical Internetworking Forum (OIF), where Ottawa’s Ranovus helped lead the co-packaging work10.
The bit leaves the switch chip
Clean signal
The chip’s SerDes sends the data out as a high-speed electrical signal.
CPO is arriving first in network switches, the “scale-out” links that tie racks together. The bigger long-term prize is putting optics directly on GPUs, so they can share data at full speed across racks. Nvidia plans to offer this option starting with its Feynman generation, expected in 202811.
Promised Gains, and the Fine Print
| The promise | The fine print |
|---|---|
| In Meta’s testing of Broadcom’s CPO switches, optics power fell 65% compared with conventional pluggables12 | It depends on the comparison. Against linear pluggable optics (LPO), which drop the DSP but stay swappable, the advantage shrinks to about 35%14. And “99.9% of all optics shipped today are still pluggables,” says Arista’s Andy Bechtolsheim15. |
| The switches ran one million cumulative port-hours without a single link dropping, and by March 2026 Meta had logged more than 50 million device-hours1213 | Much of the data comes from the lab. Meta’s results are largely from high-temperature lab testing, with one supplier (Broadcom) and one operator (Meta)14. |
| The optics sit in the switch chip’s own package, millimetres away | Repairs are harder. A pluggable can be swapped in seconds, but a failed optical engine inside a CPO package can take down 8, 16, 32 or more ports at once16. |
| Analysts expect CPO switch volumes to ramp in 2027–2028, and GPU-to-GPU optics to follow around 20292122 | Volume manufacturing is unproven. Attaching fibre to chips and testing optical engines at scale are still open problems17. |
| Capital is moving ahead of volume. Marvell agreed to pay US$3.25 billion upfront for Celestial AI, and Nvidia invested US$4 billion in Coherent and Lumentum1920 | Even Nvidia is measured. As Jensen Huang put it in August 2025, “We should stay with copper for as long as we can, and then after that, if we must, we’ll use silicon photonics”18. |
Power per 1.6T link. Nvidia figures from a December 2025 industry forum; vendor estimates.7
Energy to move one bit, in picojoules (pJ). Nvidia figures from a December 2025 industry forum; vendor estimates.7
Watts per 800 Gb/s port. Broadcom figures (vendor data) reported by The Next Platform; the pluggable range is for the same Tomahawk 4 switch.14
Canada Has Been Here Before
Ottawa–Kanata
Nortel’s Ottawa team launched the first coherent 40G optical system in 200823, and after the bust “very few people packed up shop and left town”24. That is Canada’s head start: today the CPFC makes the lasers26 for the CPO engines Ranovus packages in Kanata2728, beside Ciena, Nokia and Marvell’s optics R&D814950.
Bromont
IBM Bromont and C2MI are North America’s largest advanced packaging facility of its kind29; IBM built its CPO prototype here4 and C2MI co-develops an engine with the CPFC51. Advanced fabrication does exist in Canada, just not in the forms you typically expect.
Toronto
Celestica is a named partner on Broadcom’s Tomahawk 6 Davisson CPO switch30. POET builds optical interposer engines, mostly in the U.S. and Asia48, and Lightmatter opened an office in 202427.
Vancouver
UBC’s SiEPIC program has trained 400+ silicon photonics researchers since 200832. Coast to coast, Canada now has nearly every link of the CPO supply chain, except a leading-edge silicon fab27.
Who owns it
Ranovus, the CPFC, Celestica, C2MI and UBC are Canadian-owned or public; Ciena, Nokia, Marvell, IBM and Lightmatter answer to head offices abroad. In 2025 Alphawave Semi went to Qualcomm34 and Hyperlume to Credo35, and in one study 28 of 30 such acquisitions moved leadership out of the country36: the value of our semiconductor strengths doesn’t always stay.
Positioning for Commercialization
Canada doesn’t lack assets. The debate is how to turn them into Canadian-owned businesses. Budget 2025 had no semiconductor-specific line37, and in May 2026, AI Minister Evan Solomon ruled out a separate national semiconductor strategy38. An industry coalition counters that Canada remains “the only G7 country without a national semiconductor strategy”39.
There are four main paths that Canada can take to keep value in our nation. Each of them possess their own risks:
- Build more packaging and test capacity. Canada’s Semiconductor Council has proposed a fund of at least $3B for supply-chain facilities, including packaging and test40. However, the CSA Public Policy Centre calls building more domestic production capacity “misguided,” since most chips that enter Canada are already built into imported products41.
- Use sovereign AI compute as an anchor customer. The new $890 million government-funded AI compute program asks for Canadian supply-chain plans but sets no domestic-content rule42, and AI data centres still run on foreign GPUs.
- Commercialize public assets. This path is already in motion. In May 2026, the government announced it will spin the CPFC off as a commercial entity that must be “Canadian majority-owned”43. Ranovus has said it is interested in taking over the facility or a stake in it44, but no timeline, funding or buyer has been announced, and Sen. Colin Deacon has warned against repeating the 1989 sale of Connaught Labs45.
- Keep scale-up capital in Canada. Foreign investors supplied 80–90% of the capital in Canadian venture rounds of $50 million or more in 202546. That money brings growth now, but decision-making control shifts out of the hands of Canadians.
Every one of these paths depends on talent. ICTC’s 2025 industry mapping found “a closing window of time to pass down expertise” in areas including photonics, optical communications and advanced packaging33, with up to 20% of the workforce expected to retire within 5–10 years47.
The Opportunity for Students
CPO’s hardest remaining problems are engineering problems: designing photonic chips, attaching fibre to them reliably, managing heat, and testing optical engines before they are packaged. These draw on Electrical, Computer, Engineering Physics, Mechanical and Materials engineering, and demand is expected to ramp in the same years many of today’s undergraduates enter the workforce.
| # | Skill | From | Who hires |
|---|---|---|---|
| 1 | Photonic chip design3388 | Electrical, Eng Physics | Ranovus, Ciena, Nokia, Marvell, C2MI |
| 2 | Packaging and assembly3388 | Mechanical, Materials | Ranovus, IBM Bromont, C2MI |
| 3 | Lasers and compound semiconductors2088 | Eng Physics, Materials, Chemical | CPFC |
| 4 | Analog and mixed-signal47 | Electrical, Computer | Ciena, Nokia, Marvell |
| 5 | Test and validation88 | Electrical, Computer | Ranovus, IBM Bromont, Celestica |
| 6 | Thermal and reliability | Mechanical | Celestica |
Co-op: up to 390 placements at Ranovus, IBM and C2MI8929.
At CSSIC 2027 on January 21st in Ottawa, our keynote will cover Canada’s legacy and future in AI, photonics and hardware design. Through lab tours, the Canadian Success Showcase and our hardware hackathon, you can meet the Canadian firms currently leading CPO R&D.